1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a source voltage/substrate bias control circuit, as well as to a semiconductor storage device.
2. Related Background Art
Semiconductor integrated circuits have been under progressive miniaturization in recent years. Along with this movement, variance of semiconductor integrated circuits caused by their manufacturing processes has a large influence on capabilities of the semiconductor integrated circuits, and especially to their threshold values. The following documents disclose known techniques to cope with non-uniformity of threshold values of transistors in semiconductor integrated circuits.
“Solid-State Circuits” by Kuroda et al. in IEEE J., vol. 31, 1996 (pp 1770–1779) (herein below referred to as Non-patent Document 1) discloses a technique for controlling the threshold value of a transistor in operation as shown in FIG. 12. In this technique, a leak current monitor LCM monitors the substrate current Ichip of a transistor Tchip by way of the substrate current Imon of a transistor Tmon. Then, this technique controls the substrate current Ichip by driving a substrate bias generating circuit SSB to adjust the substrate current Imon to a target value. Thereby, the threshold value of the transistor Tchip in the chip can be controlled.
ISSCC Digest of Tech. Papers 1996 (pp 300–301) by Mizuno et al. (herein below referred to as Non-patent Document 2) discloses a technique for controlling both the threshold value of a transistor and the source voltage simultaneously as shown in FIG. 13. The control circuit controls VPP and VNN so that the semiconductor integrated circuit can obtain the maximum operation frequency.
ISSCC Digest of Tech. Papers, 2002 (pp 422–423) by Tschanz et al. (herein below referred to as Non-patent Document 3) discloses a technique for controlling the threshold value of a transistor as shown in FIG. 14. The substrate potential of a transistor TL is controlled to ensure that the semiconductor integrated circuit can obtain the maximum operation frequency.
Japanese Patent Laid-open Publication JP2002-111470-A (herein below referred to as Patent Document 1) discloses a circuit that can stabilize a uniform logical threshold voltage even under differences in operation source voltage and can input and output signals with reference to the logical threshold voltage. Thus, the circuit need not use an additional circuit such as a level conversion circuit between circuit blocks different in operation source voltage to transfer signals between them.
In general, a source voltage and a substrate bias used in a semiconductor integrated circuit are controlled to maintain a certain potential difference between them. Therefore, when the source voltage varies depending upon the operating condition, the substrate bias also varies while keeping the potential difference between the source voltage. The source voltage and the substrate bias are controlled in digital value. Heretofore, multipurpose DACs (digital-analogue converters) have been used to control the source voltage and the substrate bias in digital value.
The substrate bias generating circuit SSB disclosed by Non-patent Document 1 is under feedback control. Therefore, once the substrate current Ichip increases to a large current, the substrate bias generating circuit SSB cannot follow it, and it takes time to stabilize the substrate current Ichip. In addition, the substrate bias generating circuit SSB includes a charge pump circuit CP, and the substrate current Ichip is driven by the charge pump circuit CP as a current source. Therefore, if the substrate current Ichip becomes a large current and it takes time to stabilize the substrate current Ichip, the transistor Tchip may latch up.
The technique disclosed by Non-patent Document 2 involves the problem that the voltage source and the threshold voltage of the transistor cannot be changed independently from each other because the circuit configuration changing both VPP and VNN inevitably results in changing both the source voltage and the threshold voltage simultaneously.
In the technique shown in Non-patent Document 3, since the substrate potential of the NMOS transistor TN is near the ground potential GND, it may occur that the substrate potential required for adjusting the threshold value of the NMOS transistor TN must be a negative value. Usually, however, the semiconductor integrated circuit does not include a negative source lower than the ground potential GND. Therefore, here is the problem that, while the substrate potential of the PMOS transistor TP can be generated in the semiconductor integrated circuit, the substrate potential of the NMOS transistor TN must be introduced from outside (VBNext).
The technique disclosed by Patent Document 1 merely adjusts the threshold voltage to a certain threshold voltage, and therefore involves the same problem discussed in conjunction with Non-patent Document 3.
In case a semiconductor integrated circuit relies upon DAC for controlling the source voltage and the substrate bias used therein, the circuit needs independent DACs for the control of the source voltage and the control of the substrate bias respectively. When a semiconductor integrated circuit includes a plurality of circuit blocks different in source voltage, the circuit needs independent DACs for the control of the source voltage and the substrate bias respectively in each circuit block.